1. Field of the Invention
The inventions disclosed and taught herein relate generally to transient voltage surge suppressors; and more specifically relate to physically addressing power system modules for monitoring transient voltage surge suppressors.
2. Description of the Related Art
Many power systems, such as filters, transient voltage surge suppressors (TVSS) and uninterruptible power supplies (UPS), employ individual surge suppressors, such as metal oxide varistors (MOV), to protect the sensitive equipment they power. However, TVSS and their series fusing devices, such as MOVs, are at risk of failing due to the high current they shunt.
Therefore, such MOVs are often monitored. For example, U.S. Patent Application No. 20020024326 discloses a system that “includes: (a) in-parallel connection to an incoming power supply of a facility including a hot line and a neutral line, and at least one ground. There are components connected between the hot line and the neutral line in the following order: (b) front metal oxide varistor(s) line transient voltage surge suppressor having to suppress undesired power spikes; (c) at least one capacitor of predetermined capacitance; (d) at least two chokes in the form of inductor/metal oxide varistor transformers; (e) at least a second capacitor of its own predetermined capacitance; (f) back metal oxide varistor(S) [sic] having a predetermined capability. In preferred embodiments, the metal oxide varistor may be a plurality of varistors in parallel; (g) a failure indicator circuit connected to the transient voltage surge suppressor, including at least one relay, one voltage-surge responsive switch and one indicator signalling component.” Abstract.
However, it may be helpful to determine which MOV needs to be replaced where several MOVs are used. To this end, U.S. Pat. No. 4,626,846 discloses “[a] bus arrangement for providing equipment units with an address is disclosed. Each individual equipment unit achieves its address automatically according to its relative physical position within the organization of the units without the need for setting any switches. In simplistic terms, this is achieved by providing at each unit, modification of the bus leads. This includes the termination of one lead, the addition of one lead, and the relative repositioning of the other leads.” Abstract.
U.S. Pat. No. 5,065,154 discloses “a system comprising a plurality of digitally addressable electronic devices, all devices have the same construction and are designed for being connected in series to a common central monitoring station. The addressing of these devices is accomplished by a plurality of address lines which are connected to input contacts of the respective device. Within each device, a selection gate is connected to the input contacts which provides an enabling signal if the signal on said address lines has a predetermined bit pattern. Each device has output contacts connected to its input contacts to which the input contacts of a next device are connected. The address lines are connected from the input contacts to the output contacts of the device in such a way that the contacts are interchanged, and an inverter is inserted in one of said lines so that the bit pattern forming the address provided at the output contacts is different from the bit pattern received at the input contacts. Thus, along the system of series connected devices a plurality of different bit patterns is produced so that the position of the correct bit pattern to which the device selection means responds, is shifted along the series connected devices in order to address the device which is in a predetermined position. A preferred application of such devices is in medical surveillance systems in which a plurality of racks are connected serially together and to a center monitoring station, each rack being allocated to a different task and including the units which are needed to monitor the vital functions of a patient required for that task.” Abstract.
U.S. Pat. No. 5,262,771 discloses “a method for addressing processor units of an equipment for monitoring and/or controlling, whereby a polling unit and processor units (6) provided with addresses exchange information, the processor units (6) are automatically addressed with the assistance of addressing telegrams in that an address contained in the addressing telegram is respectively incremented. The method can be advantageously used in equipment for in-service monitoring of equipment of communication transmission technology.” Abstract.
U.S. Pat. No. 5,553,258 discloses “a method and apparatus for performing exchange transactions between caches and a main memory of a computer system, the caches and main memory being coupled to one another by a bus. The method includes the steps of providing caches of different sizes with a cache having a smallest size, and with each cache having an index fixed as a function of the size of the cache. For each exchange transaction, the number of bits of an index used to address a selected cache location are determined, and the upper bits of a memory address from a tag store location corresponding to the selected cache location are retrieved, where the retrieved upper address bits form an exchange address. In the event that the index of the selected cache location comprises more bits than the index of the cache having the fewest addressable locations, the excess bits of the index of the selected cache location are appended to the exchange address. The cache then transmits the exchange address, a memory read address, and exchange data to memory.” Abstract.
U.S. Pat. No. 5,576,698 discloses “[a]n array of like system modules linked to a common control unit by connect lines, bussed and connected to all the modules by respective removable pin units so that each module address can be generated solely according to which said pin units are not connected.” Abstract.
The inventions disclosed and taught herein are directed to an improved system for physically addressing modules for monitoring transient voltage surge suppressors.